Design of Digital Clock Calendar Using Fpga

First, experimental tasks

The multi-function digital clock is implemented with the FPGA device and EDA technology.

basic skills:

1. When displayed in digital form, the time, second;

2, the hour counter is synchronized 24);

3. Require manual time, the calibration.

extensions:

1, any time alarm clock;

2, hour display (12/24) switching circuit

3, the imitation radio station is reporting;

4, automatic reporting time number.

Second, experimental requirements

1, familiar with the use of EDA software;

2, the formation block diagram of the digital clock, dividing the module;

3. Design circuit by dividing module, hierarchical method;

4. Design and simulation of each unit module circuit;

5. Design and simulation of the overall circuit;

6. Download and debugging of the overall circuit.

7. Design can use a schematic or HDL language

Third, the experimental environment

1.Windows10 operating system

2. ISE software vivado2020.2

3.FPGA experiment development device Nexys4-DDR

Fourth, digital clock design and composition block diagram

The multi-function digital clock designed is divided into two parts of the main circuit and the extended circuit, wherein the main circuit is divided into counter module, display module, calorie module, and extended circuits are divided into an alarm module and the imitation station positive report. At 100 MHz CP signal excitation, the host circuit counter module is output from the register in the alarm module separately outputs the BCD code corresponding to the time division, and the display module is input via the data selector, and the BCD code decodes the digital tube corresponding to the digital tube. Dynamic scanning through 500 Hz Maping Digital Tube Coding through the bus is mapped to the corresponding bit digital tube to achieve the multiplexing of the decoder and the output port. The alarm module compares the BCD code alarm counter in the main circuit counter module underlying register, and the same amount of 1 second 500 Hz of 1 second is generated. At the time of the news, the main circuit counter is reported to the BCD code in the underlying register of the main circuit counter module with the newsmill time, 59 minutes, 57 seconds, 53 seconds, 55 seconds, 57 seconds, generates a bass of 1 second 500 Hz at each hour. The 1 second 1000 Hz treble prompt was generated in 59 seconds has arrived, and thereafter produced 500 Hz bass of the corresponding hour number.

In summary, the multi-function digital clock composition is shown below:

Figure 1 Multi-function digital clock composition block diagram

V. Split Structure Source Code Design and Comment

Multi-function digital clock module design as follows:

Figure 2 Multi-function digital clock module design composition map

The MIPS assembly language source program division module is designed as follows:

(1) Main circuit counter module

The main circuit counter module is mainly composed of a divider, a mold 60 counter, a model 24 counter, with the die 60 counter consisting of a mold 10 counter and a die 6 counter. The 100MHz clock signal CP is determined by a 1 Hz clock signal induces a two-mode 60 counter, respectively, and the number of counts, respectively, count, respectively, counts the time count. The second counter enables constant effectiveness, and the countercarrier enables valid when the second counter value is 59 or when the score signal is valid, when the counter is valid when it is valid when the counter, the secondary counter is 59 or when the signal is valid. When the system is normal timing in the display time mode, it can be effectively implemented by changing the score, whether the timing function is effectively implemented. In addition, the 12-hour / 24 hours mode switch is implemented by the mode conversion button, and only the model 24 counter is used, so the conversion relationship between 24 hours and 12 can be obtained directly to the output of 12 hours. The overall level is as follows:

Figure 3 Overall relationship between main circuit counters

Each counter is implemented based on four-bit output counter such as a mold 10 counter or a mold 6 counter, and each module Verilog source code is as follows:

          Module Freq_divider (// Division      input CP100M,      output reg CP1      );      integer i,j;         initial begin            j=0;            CP1=0;      end         always @(posedge CP100M)                begin                       j <= j + 1;                       if(j==32'd49999999)                              begin j <= 1'b0; CP1 <= ~CP1; end                     end  endmodule

The code related to the main partial timer in the top module is as follows:

          FREQ_DIVIDER (CP, CP1); // Division   Counter60 U0 (NCR, EN, CP1, Second [7: 0]); // Second Variable 60 Enciprometer   Counter60 U1 (NCR, min_en && en, cp1, minute [7: 0]); // divided variable 60 credit counter      assign min_EN=Adj_Min ? Vdd && ~alarm_clock:(second==8'h59);   // Differential in position signal, if the score enables effective and the alarm is invalid, the carry enables valid. If the score is invalid but the second variable is 59, the inlet enable can be effective      counter24 u2(nCR,hour_EN && EN,CP1,hour[7:0]);   // Time Variable 24 Enter Counter      assign hour_EN=Adj_Hour ? Vdd && ~alarm_clock:((minute == 8'h59) && (second == 8'h59));   // The carry signal, if the time is invalid, the alarm is invalid, and the carry enables it. If you are invalid, if you are invalid, the divisor and second variable are 59, the carry enables effective   // Digital clock body part

(2) Alarm timing counter module

The overall hierarchical relationship is basically the same as the main circuit counter module. Different are the three-level counter enable signals of the alarm timing counter module need to be in touch with the alarm signal ALARM_CLOCK.

The code related to the main partial timer in the top module is as follows:

          counter60 a0(nCR,alarm_clock,CP1,second_alarm[7:0]);      counter60 a1(nCR,minalarm_EN && alarm_clock,CP1,minute_alarm[7:0]);      assign minalarm_EN=Adj_Min ? Vdd:(second_alarm==8'h59);      counter24 a2(nCR,houralarm_EN && alarm_clock,CP1,hour_alarm[7:0]);      assign houralarm_EN=Adj_Hour ? Vdd:((minute_alarm == 8'h59) && (second_alarm == 8'h59));   // When the alarm is invalid, the original signal is directly acting on the alarm timing variable.   // Alarm main body

          Module Counter60 (//60 Bundry Counter      input nCR,      input EN,      input CP,      output wire [7:0] Cnt      );      wire ENP;   Counter10 UC0 (NCR, EN, CP, CNT [3: 0]); // Delivery of the counter   Counter6 UC1 (NCR, ENP, CP, CNT [7: 4]); // Ten of the counter   Assign Enp = (CNT [3: 0] == 4'H9) & en; // Generates the set of ten bits of the counter  endmodule

          Module Counter10 (// 10 Bundry Counter      input nCR,      input EN,      input CP,      output reg [3:0] Q      );      initial begin          Q=4'b0000;      end      always @(posedge CP or negedge nCR)          begin   IF (~ ncr) q <= 4'b0000; // ncr = 0, counter is clearly cleared   Else if (~ en) q <= q; // en = 0, pause count          else if(Q == 4'b1001) Q <= 4'b0000;   Else Q <= Q + 1'b1; // Counter increases 1 count          end  endmodule

          Module Counter6 (//6 Billing Counter      input nCR,      input EN,      input CP,      output reg [3:0] Q      );      initial begin          Q=4'b0000;      end      always @(posedge CP or negedge nCR)          begin   IF (~ ncr) q <= 4'b0000; // ncr = 0, counter is clearly cleared   Else if (~ en) q <= q; // en = 0, pause count          else if(Q == 4'b0101) Q <= 4'b0000;   Else Q <= Q + 1'b1; // Counter increases 1 count          end  endmodule

          module counter24(     input nCR,     input EN,     input CP,     output reg [7:0] Q     );     wire ENP;     initial begin         Q = 8'b00000000;     end      always @(posedge CP or negedge nCR)         begin                          If (~ ncr) q [7: 0] <= 8'b00000000; // ncr = 0, the counter is asynchronous                          Else if (~ en) q <= q; // en = 0, pause count             else if(Q[7:0] == 8'b00100011) Q[7:0] <= 8'b00000000;             else if(Q[3:0] == 4'b1001)                 begin                  Q[3:0] <= 4'b0000;                  Q[7:4] <= Q[7:4] + 1'b1;                 end                          Else Q <= Q + 1'b1; // Counter increases 1 count         end          endmodule

(3) Display module

The display module consists of a BCD-Digital Tube Decoder, a displacement register, and multiplexer. The working principle of the display module is based on the human eye visual temporary effect. The 4-bit BCD code data in 6 pieces is input to the decoder by multiplexer. The code is driven to the 8-digit code to drive 6 pieces of digital tube. Cathode pins, the common anode is driven by the displacement register, and dynamically scanned each tablet in turn. The overall level is as follows:

Figure 3 shows the overall level of modules

The digital tube decoder is designed as:

          module decoder(      input [3:0] I,      output reg [7:0] Y      );       always @(*) begin                casex(I)                              4'b0000: Y = 8'b11000000;    //0                        4'b0001: Y = 8'b11111001;    //1                        4'b0010: Y = 8'b10100100;    //2                        4'b0011: Y = 8'b10110000;    //3                        4'b0100: Y = 8'b10011001;    //4                        4'b0101: Y = 8'b10010010;    //5                        4'b0110: Y = 8'b10000010;    //6                        4'b0111: Y = 8'b11111000;    //7                        4'b1000: Y = 8'b10000000;    //8                        4'b1001: Y = 8'b10010000;    //9                        4'b1010: Y = 8'b10001000;    //A                        4'b1011: Y = 8'b10000011;    //b                        4'b1100: Y = 8'b11000110;    //C                        4'b1101: Y = 8'b10100001;    //d                        4'b1110: Y = 8'b10000110;    //E                        4'b1111: Y = 8'b10001110;    //F                endcase       end  endmodule

The displacement register is designed, where freq_divider2 is 500 Hz scanning CP signal:

          module shift(      input CLK,      output reg[7:0] AN      );      wire CP;      initial begin          AN <= 8'b1111_1110;      end  FREQ_DIVIDER2 SDIVIDER_U0 (CLK, CP); // Division      always @(posedge CP) begin   AN [5: 0] <= {an [0], AN [5: 1]}; // cycle displacement      end  endmodule

The multiplexer is designed as follows:

          module switch(   INPUT [63: 0] i, // 6-terminal 8 digit tube splicing   INPUT [7: 0] an, // shift register output      output reg [7:0] BCD      );   Always @ (*) begin // A [i] loop displacement and selection of input signals          if(~AN[0])     BCD <= I[7:0];          else if(~AN[1])BCD <= I[15:8];          else if(~AN[2])BCD <= I[23:16];          else if(~AN[3])BCD <= I[31:24];          else if(~AN[4])BCD <= I[39:32];          else if(~AN[5])BCD <= I[47:40];          else if(~AN[6])BCD <= I[55:48];          else if(~AN[7])BCD <= I[63:56];          end  endmodule

Scanning The top layer module is as follows:

          module scan(      input [23:0] I,      input CLK,      output wire [7:0] Y,      output wire [7:0] AN      );      wire [3:0]BCD;   Shift Shift_U0 (CLK, AN); / / Displacement Register   Switch Switch_u0 (i, an, bcd); // Data Distributor   Decoder Decoder_U0 (BCD, Y); // BCD Digital Decoder  endmodule

The digital clock top layer implements loop scan by calling the SCAN function:

          scan( scanner, CP , Y[7:0], AN[7:0]);   // Scanner is the output display BCD code from the alarm clock or clock 12/24 time to select multiple times.   // y is the anode signal from the scanned   // AN is a cathode signal obtained by scanning

(4) Audio module (alarm or imitation station is reported when reported to the whole point)

The alarm module of multi-function digital clock is reported to the intensity of the Audio output to invigo the audio output pin of the FPGA experiment board to implement the audio output, and play it with an external headset. The design requirement of the module is valid when the alarm audio signal is valid, the output is 1 second, the time is 1 second 500Hz audio signal to the audio output pin; 59 minutes and 57 seconds, 53 seconds, 55 seconds, and 57 seconds The duration of a second and a second time for a second time in 59 seconds, it achieves a positive report; generates low-frequency sound sound, and hold time 1s, and interval time 1s at the time of entering the next hour. The audio control module Verilog code is as follows:

          module baoshi(CP1,CP100M,hour,second,second_alarm,minute,AUD_PWM,alarm);   / / Enter 1Hz, 100MHz CP signal, the timing of the main body clock, the bcd code, the second BCD code of the alarm module, the audio output, the alarm enable signal  input [7:0]hour,minute,second,second_alarm;  input CP1,CP100M;   Input alarm; // alarm clock signal  output reg AUD_PWM;  wire CP1K,CP500;    freq_divider3 f0(CP100M,CP500,CP1K);   // Division 3, divided 100 MHz signal into audio signals of 500 Hz and 1000 Hz    [email protected](CP1) begin                if(alarm)   // Alarm enable signal is valid                       begin                           if(second[0] == second_alarm[0]) AUD_PWM <= CP500;   / / Directly give 500 Hz audio signals to audio output directly when the main module is equal to the lowest position of the second counter of the alarm module                           else AUD_PWM <= 0;   // No sound when you wait                       end   Else IF (Minute == 'D89) // When 59 minutes                       begin                              if(second == 'd83 || second == 'd85 || second == 'd87 || second == 'd81)                                     AUD_PWM <= CP500;   // 53, 55, 57, 51 seconds 500Hz bass signal input                              else if(second == 'd89)                                     AUD_PWM <= CP1K;   // 59 seconds to input 1000 Hz treble signal input                              else                                     AUD_PWM <= 'd0;   // Other time no sound                       end   Else IF ((hours == 0 || Hour == 'D18) && minute ==' d0) // 12 points knock 12                begin                 if(second <= 'd34)begin                      if (second[0] == 0) AUD_PWM <= CP500;                      else AUD_PWM <= 'd0;                  end                   end                else if(minute == 'd0 && second[7:4]*10 + second[3:0] <= 2*((hour[3:0]+hour[5:4]*10)%12)-1'b1 ) begin   // At the time of the news, when the value of the main body module second counter is less than 2 * (time% 12) -1, the report of the number of specified times is just realized.                    if (second[0] == 0) begin                      AUD_PWM <= CP500;   / / Low of 0 hours                    end                    else AUD_PWM <= 'd0;                end                else AUD_PWM <= 'd0;         end  endmodule

Call the Baoshi function in the top module to implement audio control

          baoshi(CP1,CP,hour,second,second_alarm,minute,AUD_PWM,alarm);   // 1 Hz CP signal   // 100MHz CP signal   // Time Net Counter   // Alarm clock counter   // Audio output variable   // Alarm enable signal

(5) Top module

The top module input is: clear end, enable end, score, tuning, alarm adjustment, alarm switch, 12, 24, 100MHz clock signal CP.

Output: audio output, seven-stage digital tube anode signal, cathode signal

Call the divider 1 to get a 1 Hz clock; call 60 credits and 24-enrichment counter to implement the main module and the count of the alarm module, call the SCAN function scan display, call the baoshi function to implement audio control

The main module completes the logical function:

1. Display BCD code Scanner [7: 0] by multiple selection of alarm clock or clock 12/24

2. Get alarm audio signal ALARM by comparing clock body counters and alarm counter

          module top_clock(   Input alarm_clock, alarm_switch, // The input control signal of the alarm is the alarm time and the alarm switch.   Output Wire AUD_PWM, // Alarm Sound Signal Output to Headphone Interface   Input CP, // Enter the 100MHz clock signal of FPGA standby   Input NCR, En, // Clear end, enable   Input adj_min, adj_Hour, trans, // divided adjustment, time adjustment, 12-24 hours conversion   Output Wire [7: 0] y, [7: 0] an // y is the display result of the seven-stage digital tube, and an AN is selected in 8 digital tubes.      );   REG [23: 0] scanner; // scanner is 6-digit data output signal, used as a scan output   Wire [7: 0] Hour, minute, second; // top module time second Wire variable   Wire [7: 0] Hour_Alarm, Minute_Alarm, SECOND_ALARM; / / Top Wire Variable   Supply1 VDD; // High level   Wire min_en, hour_en, minalarm_en, hourarm_en; // time division, and alarm time division enable signal   Wire CP1; // 1Hz clock signal   FREQ_DIVIDER (CP, CP1); // Division   REG ALARM; // Alarm built-in switch register variable      initial begin   Alarm = 0; // initially alarm clock      end   Counter60 U0 (NCR, EN, CP1, Second [7: 0]); // Second Variable 60 Enciprometer   Counter60 U1 (NCR, min_en && en, cp1, minute [7: 0]); // divided variable 60 credit counter      assign min_EN=Adj_Min ? Vdd && ~alarm_clock:(second==8'h59);   // Differential in position signal, if the score enables effective and the alarm is invalid, the carry enables valid. If the score is invalid but the second variable is 59, the inlet enable can be effective      counter24 u2(nCR,hour_EN && EN,CP1,hour[7:0]);   // Time Variable 24 Enter Counter      assign hour_EN=Adj_Hour ? Vdd && ~alarm_clock:((minute == 8'h59) && (second == 8'h59));   // The carry signal, if the time is invalid, the alarm is invalid, and the carry enables it. If the invalidation is invalid, the part varies is 59, the carry enables effective   // Digital clock body part           counter60 a0(nCR,alarm_clock,CP1,second_alarm[7:0]);      counter60 a1(nCR,minalarm_EN && alarm_clock,CP1,minute_alarm[7:0]);      assign minalarm_EN=Adj_Min ? Vdd:(second_alarm==8'h59);      counter24 a2(nCR,houralarm_EN && alarm_clock,CP1,hour_alarm[7:0]);      assign houralarm_EN=Adj_Hour ? Vdd:((minute_alarm == 8'h59) && (second_alarm == 8'h59));   // When the alarm is invalid, the original signal is directly acting on the alarm timing variable.   // Alarm main body           always @(*) begin      if (alarm_clock == 0) begin   // Alarm Timed signal invalid, output clock body counter module          if(trans && hour[7:0] == 8'b00000000) scanner = {8'b00010010, minute[7:0], second[7:0]};   // TRANS Time Conversion Signal is valid, and is 0 points of 24 hours, and the output is 12 hours.          else if(trans && hour[7:0] > 8'b00010010 ) scanner = {hour[7:0]-8'b00010010, minute[7:0], second[7:0]};   // TRANS Time Conversion Signal is valid, when the output 24 time is displayed - 12          else scanner = {hour[7:0], minute[7:0], second[7:0]};   // TRANS Time Conversion Signal is invalid, and the time counter time is displayed in the output 24 time.      end   Else Begin // Alarm Timed Signal Valid, Output Clock Counter Module          if(trans && hour_alarm[7:0] == 8'b00000000) scanner = {8'b00010010, minute_alarm[7:0], second_alarm[7:0]};   // TRANS Time Conversion Signal is valid, and is 0 points of 24 hours, and the output is 12 hours.          else if(trans && hour_alarm[7:0] > 8'b00010010) scanner = {hour_alarm[7:0]-8'b00010010, minute_alarm[7:0], second_alarm[7:0]};   // TRANS Time Conversion Signal is valid, when the output 24 time is displayed - 12          else scanner = {hour_alarm[7:0], minute_alarm[7:0], second_alarm[7:0]};   // TRANS Time Conversion Signal is invalid, and the time counter time is displayed in the output 24 time.      end           if ({hour[7:0], minute[7:0], second[7:0]} == {hour_alarm[7:0], minute_alarm[7:0], second_alarm[7:0]} && (alarm_switch == 1))          alarm = 1;   // Alarm module is effective, the clock body counter is the same as the alarm counter, the alarm audio signal is effective      else if(alarm_switch == 0) alarm = 0;   // Alarm part      end           scan( scanner, CP , Y[7:0], AN[7:0]);   // Scanner is a 12/24 time of the alarm or clock that selects the resulting alarm or clock to display the BCD code.  // y is the anode signal from the scanned   // AN is a cathode signal obtained by scanning      baoshi(CP1,CP,hour,second,second_alarm,minute,AUD_PWM,alarm);   // 1 Hz CP signal   // 100MHz CP signal   // Time Net Counter   // Alarm clock counter   // Audio output variable   // Alarm enable signal  endmodule

6) Pin constraint

          set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33 } [get_ports { Y[7] }]; #IO_L24N_T3_A00_D16_14 Sch=ca  set_property -dict { PACKAGE_PIN R10   IOSTANDARD LVCMOS33 } [get_ports { Y[6] }]; #IO_25_14 Sch=cb  set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { Y[5] }]; #IO_25_15 Sch=cc  set_property -dict { PACKAGE_PIN K13   IOSTANDARD LVCMOS33 } [get_ports { Y[4] }]; #IO_L17P_T2_A26_15 Sch=cd  set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { Y[3] }]; #IO_L13P_T2_MRCC_14 Sch=ce  set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { Y[2] }]; #IO_L19P_T3_A10_D26_14 Sch=cf  set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { Y[1] }]; #IO_L4P_T0_D04_14 Sch=cg  set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { Y[0] }]; #IO_L19N_T3_A21_VREF_15 Sch=dp   #        set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]  set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]  set_property -dict { PACKAGE_PIN T9    IOSTANDARD LVCMOS33 } [get_ports { AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]  set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]  set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]  set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33 } [get_ports { AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]  set_property -dict { PACKAGE_PIN K2    IOSTANDARD LVCMOS33 } [get_ports { AN[6] }]; #IO_L23P_T3_35 Sch=an[6]  set_property -dict { PACKAGE_PIN U13   IOSTANDARD LVCMOS33 } [get_ports { AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]   #          set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets alarm_switch_IBUF]  set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { CP}]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz   # 100MHz Clock Signal CP    set_property -dict { PACKAGE_PIN A11   IOSTANDARD LVCMOS33 } [get_ports { AUD_PWM }]; #IO_L4N_T0_15 Sch=aud_pwm   #            set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { nCR }]; #IO_L24N_T3_RS0_15 Sch=sw[0]  set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { EN }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]  set_property -dict { PACKAGE_PIN M13   IOSTANDARD LVCMOS33 } [get_ports { Adj_Min }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]  set_property -dict { PACKAGE_PIN R15   IOSTANDARD LVCMOS33 } [get_ports { Adj_Hour}]; #IO_L13N_T2_MRCC_14 Sch=sw[3]  set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { alarm_clock }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]  set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports { alarm_switch }]; #IO_L7N_T1_D10_14 Sch=sw[5]  set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { trans }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]   #  ,,    , enable the energy, score, adjustment, the alarm, the alarm switch, 12, 24 hours conversion

6. Implementation process

1 )mold 60 Design and Simulation of Counters

Overall simulation, call up the 60-enrichment counter module